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Deeply Pipelined Digit-Serial LDPC Decoding
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DOI：10.1109/TCSI.2012.2206461.png)
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Highly parallel VLSI implementations of low-density parity-check (LDPC) decoders have a large number of interconnections, which can result in designs with low logic density. Bit-serial architectures have been developed that reduce the number of wires needed, however, they do not fully realize the potential for deeply pipelined serial data processing. Digit-online arithmetic allows operations to be performed in a serial, digit-by-digit manner, making it ideal for use in implementing a digit-serial LDPC decoder. Digit-online circuits for the primitive operations required for an offset min-sum LDPC decoder are simple, and allow deep pipelining at the digit level. A new hardware architecture for LDPC decoding is demonstrated, using redundant number systems for the internal representation of values. We present post-layout decoder results for the (2048, 1723) 10GBASE-T LDPC code in a general-purpose 65 nm CMOS technology. The decoder requires a core area of 10.89 mm(2) and operates at a clock frequency of 980 MHz. The decoder can simultaneously decode two 4-bit frames at 41.8 Gbit/s or one 10-bit frame at 20.9 Gbit/s.
Keyword:
Forward error control (FEC)
iterative decoder architecture
low-density parity-check (LDPC) codes
message-passing decoding
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