.png){kind=icon}
返回
Dynamic Programming Networks for Large-Scale 3D Chip Integration
.png){kind=icon}
PRE
AI
DOI：10.1109/MCAS.2011.942102.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
Recent technological advance in three-dimensional (3-D) on-chip systems integration provides a promising platform to realize multicore, multiprocessor, and networks-on-chip (NoC) based systems with augmented performance. With the additional tightly coupled physical layers, onchip system complexity grows significantly. The provision for efficient run-time management in large-scale system becomes critical. In this article, we review the design of an emerging on-chip dynamic-programming (DP) network [3] [5], of which the capabilities have been demonstrated in a range of applications including optimal paths planning [6], dynamic routing [5] and deadlock detection [2]. A design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3-D) architecture using through-silicon-via (TSV) CMOS technology [1], is also presented. The vertical inter-layer communication is achieved by the means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. Testing results demonstrated the effectiveness of such approach for deadlock detection and the minuscule computational delay for detecting deadlock from a large-scale network.
AI总结
对已上传原文的论文进行重点信息的提取，主要内容包括：简要概述、研究摘要、背景介绍、关键亮点、图文解析、展望与总结。
期刊
IF:
3.5
论文数:
530
被引数:
1.3K
机构
引用论文
.png){kind=icon}
分享收藏分享收藏
查看更多内容