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Energy-efficient multiprocessor systems-on-chip for embedded computing: Exploring programming models and their architectural support
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DOI：10.1109/TC.2007.1040.png)
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In today's multiprocessor SoCs (MPSoCs), parallel programming models are needed to fully exploit hardware capabilities and to achieve the 100 Gops/W energy efficiency target required for Ambient Intelligence Applications. However, mapping abstract programming models onto tightly power-constrained hardware architectures imposes overheads which might seriously compromise performance and energy efficiency. The objective of this work is to perform a comparative analysis of message passing versus shared memory as programming models for single-chip multiprocessor platforms. Our analysis is carried out from a hardware-software viewpoint: We carefully tune hardware architectures and software libraries for each programming model. We analyze representative application kernels from the multimedia domain, and identify application-level parameters that heavily influence performance and energy efficiency. Then, we formulate guidelines for the selection of the most appropriate programming model and its architectural support.
Keyword:
MPSoCs
embedded multimedia
programming models
task-level parallelism
energy efficiency
low power
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3.8
论文数:
5.4K
被引数:
9.8K
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