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Experiments of a Novel Junction Field-Effect Transistor With Dual-Controlled 3-D Gates
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DOI：10.1109/ted.2026.3704327.png)
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Abstract
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A novel junction field-effect transistor with dual-controlled, 3-D gates (DG JFET) is proposed and experimentally demonstrated in this article. The proposed device features a dual-gate (G) architecture comprising a variable G and a fixed G, enabling the design of the pinch-off region (PR) and the voltage-blocking region (VB-R) of the DG JFET independently without mutual interference. The PR operates in an omnidirectional 3-D depletion mode, and the pinch-off voltage can be flexibly modulated by varying the voltage applied to the variable gate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {g}}$ </tex-math></inline-formula> without degrading the breakdown voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {B}}$ </tex-math></inline-formula> or device reliability. Experimental verification shows that the breakdown voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {B}}$ </tex-math></inline-formula> of the DG JFET remains stably above 820 V while the pinch-off voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {off}}$ </tex-math></inline-formula> is tuned within the range of 20–40 V, in contrast to conventional structures where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {B}}$ </tex-math></inline-formula> fluctuates with variations in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {off}}$ </tex-math></inline-formula>. The measured DG JFET exhibits a higher <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state breakdown voltage and a larger current-drive capability compared with its conventional counterpart, owing to the alleviated Kirk effect. Finally, 320 dies of both the DG JFET and the conventional structure were subjected to reliability testing at an elevated temperature of 150° under a drain bias <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {D}}$ </tex-math></inline-formula> of 560 V. All 320 DG JFET devices passed the stress test, with only a 4.7% degradation in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {B}}$ </tex-math></inline-formula>, demonstrating significantly enhanced stability relative to conventional JFETs, which exhibited a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {B}}$ </tex-math></inline-formula> degradation of 11%. The DG JFET has been successfully mass produced at Central Semiconductor Manufacturing Corporation (CSMC).
Keywords:
Breakdown voltage
junction field-effect transistor with dual-controlled 3-D gates (DG JFET)
omnidirectional 3-D depletion
pinch-off voltage
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3.2
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685
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3.7W
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