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Fabrication and Characterizations of High-Aspect-Ratio TSVs With Low Parasitic Parameters for High-Density 3-D Integration
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DOI：10.1109/ted.2026.3707076.png)
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Abstract
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High-aspect-ratio through-silicon vias (TSVs) with a small diameter are favorable for heterogeneous 3-D integration by providing a higher interconnection density. In this article, we present a simplified process flow for fabricating TSVs with a diameter of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{6}~\mu $ </tex-math></inline-formula>m and an aspect ratio of up to 15:1. Parylene-C formed by chemical vapor deposition (CVD) is used as the TSV liner, which shows a high step coverage exceeding 47%. Subsequently, a continuous Cu seed layer is deposited through combined presputtering and electroless plating (ELP) incorporating with ultrasound treatment. Finally, void-free Cu pillars are fabricated by electroplating, and the redistribution layer (RDL) is formed by a simple wet-etching step. The whole process flow is low-temperature, and the electrical characterizations demonstrate that the fabricated TSVs have low parasitic parameters. Particularly, the leakage current from an as-fabricated TSV to the substrate is only 33 fA at 20 V. Moreover, the parasitic capacitance of an as-fabricated TSV is only 65 fF in the accumulation region and 38 fF in the depletion region with a hysteresis of 1.5 V, which decreases to 500 mV after heat treatment at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{200}~^{\circ}$ </tex-math></inline-formula>C for 1 h. Furthermore, the fabricated TSV exhibits an insertion loss below 0.5 dB and a return loss exceeding 15 dB across the 1 GHz–30 GHz range. The low parasitic parameters and good high-frequency performance further ensure the feasibility of the presented high-aspect-ratio TSVs in providing reliable electrical interconnects for high-density 3-D integration applications.
Keywords:
3-D integration
high-aspect-ratio through-silicon vias (TSVs)
low leakage current
low parasitic capacitance
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