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Fast Hardware Architecture for 2-D Separable Convolution Operations
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DOI：10.1109/TCSII.2018.2819187.png)
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摘要
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2-D convolution is a widely used low-level image processing operation, especially in spatial filtering, sharpening, and edge detection. Real-time implementation of the convolution operation is a challenging task due to its increasing computational cost with increasing kernel and input image size. This brief focuses on the real-time implementation of a separable convolution operation based on distributed arithmetic with support for processing high-resolution images using large size kernel. The architecture processes pixels immediately whenever available from external memory, achieving low processing time compared to existing works. Two FPGA architectures, namely single window separable convolution (SWSC) architecture and multi-window separable convolution (MWSC) architecture, are proposed. These architectures are realized based on concurrent access of stored pixels and parallel processing of overlapped window in order to attain higher performance/area utilization. Implementation results show that SWSC architecture achieves better processing time and area utilization at the cost of lower throughput compared to MWSC architecture.
Keyword:
Separable convolution
distributed arithmetic
FPGA
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