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Fast Yield Analysis and Optimization Based on Sensitivity and Orthogonal Sampling
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DOI：10.1109/TCAD.2025.3586887.png)
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Process variations in advanced integrated circuit pose significant challenges for robust system design. This brief presents a novel fast Monte Carlo (FMC) low-sigma yield analysis method for various digital, analog, and mixed-signal circuits. The FMC approach employs a quadratic surrogate model based on sensitivity analysis to minimize simulation overhead, while incorporating a finite difference with orthogonal sampling (FDOS) technique that significantly reduces time complexity compared to the conventional finite difference method (FDM), especially in high-dimensional parameter spaces. Additionally, sensitivity differential evolution FMC (SDEFMC) method is proposed, which employs a hybrid yield optimization framework, along with a comprehensive sorting strategy and a relative constraint violation (RCV)-based selection technique to expedite the search for optimal design. Experiments on real-world circuits with tens to hundreds of parameters show that FMC achieves $75 \times $ to $207 \times $ speedup over Monte Carlo (MC) while maintaining high accuracy, and SDEFMC delivers $4.0 \times $ to $25.5 \times $ speedup with notable yield improvements compared to existing approaches, demonstrating the potential for large-scale circuit applications.
Keyword:
High-dimensional space
hybrid framework
orthogonal sampling
sensitivity analysis
surrogate model
期刊
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2.9
论文数:
671
被引数:
9.6K
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