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Hardware Optimized Modular Reduction

delete2025-01-29
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OA
AI
A
Alexander Magyari *
Y
Yuhua Chen
DOI：10.3390/electronics14030550delete
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摘要

摘要

En 中文
我们介绍了一种针对硬件优化的模约减方法，该方法优于传统方法。通过利用计算得到的约减周期和组合逻辑，我们实现了功耗降低30%、可配置逻辑块（CLBs）减少27%以及查找表（LUTs）减少42%，相比传统实现方案。我们的硬件优化模约减（HOM-R）系统可以在单个250 MHz时钟周期内将256位输入压缩到四位基。此外，我们的方法通过消除对乘法器或除法器的需求，仅依赖加法和可定制LUTs，从而区别于Barrett和Montgomery约减等主流技术。这种创新方法释放了通常被高功耗DSP占用的FPGA资源，为各类设计需求提供了极具吸引力的低功耗、低延迟替代方案。
Keyword:
PQC
FPGA
cryptography
modular
reduction

期刊

Electronics 封面图
Electronics
IF:
2.6
论文数:
1.0W
被引数:
4.7W

机构

U
Univ Houston
学者数:
693
论文数: 383
被引数: 115
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