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In-Memory Logic Operation Based on a Novel Spin-Orbit Torque MRAM
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DOI：10.1109/LED.2025.3607381.png)
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Abstract
En 中文
Spin-orbit torque (SOT)-based in-memory logic designs offer a promising approach to alleviating the memory wall problem. However, in existing schemes, the basic cells mainly rely on auxiliary physical mechanisms or transistors, which considerably limit their applicability. In this work, we demonstrate a novel SOT-based device fabricated on an 8-inch wafer platform, featuring dual canted magnetic tunnel junctions (MTJs) monolithically integrated via a well-designed SOT channel. This device breakthrough simultaneously achieves fast switching (current density is 19.8 MA/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>@5 ns), multi-bit storage, and in-memory logic operations via SOT alone, while maintaining compatibility with CMOS technology (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma \%$ </tex-math></inline-formula> under 7.25% in arrays). By exploiting synergistic voltage control, we achieve <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> XOR operation and edge detection with error tolerance and competitive F-measure. Our proposed scheme provides a potential pathway toward next-generation large-scale, ultra-fast, and energy-efficient in-memory logic.
Keywords:
Spin-orbit torque
dual canted magnetic tunnel junctions
in-memory logic
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