.png){kind=icon}
.png){kind=icon}
Return
Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked SRAM Architecture
.png){kind=icon}
PRE
AI
P
L
Z
Y
蒋
Q
Z
N
DOI：10.1109/TCAD.2025.3607137.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
While 3D-stacked static random-access memory (SRAM) architectures have demonstrated prominent performance speedup for tensor computing by exploiting higher bandwidth, larger buffer, and reduced latency, they suffer from thermal challenges owing to the vertical stacking nature of chips. In this article, we identify that tensor dataflow may further exacerbate the thermal issues, so we propose T3D, the first thermal-aware tensor framework for 3D-stacked SRAM architectures, leveraging tensor dataflow characteristics to significantly enhance thermal performance. Specifically, we first perform a quantitative formulation to identify the most energy-efficient tensor dataflow with given 3-D constraints, effectively reducing heat generation without performance loss. Then, we develop a thermal-aware 3-D architectural floor plan to improve heat spreading by optimizing the spatial arrangement of multiple SRAM macros with varying power overheads, which is caused by mismatched data access rates of tensor computing. Experimental results show that our proposed T3D can reduce the peak chip temperature by 12.9C on certain LLM and DNN workloads over the state-of-the-art 3-D solutions.
Keywords:
Random access memory
Three-dimensional displays
Tensors
Computer architecture
Organizations
Bandwidth
Optimization
Stacking
Heating systems
Energy efficiency
3D-stacked static random-access memory (SRAM) architectures
architectural floor plan
energy efficiency
tensor dataflow
thermal issue
Journal
I
IF:
2.9
Papers:
564
Citations:
9.6K
Organization
Cited Papers