Multioperand parallel decimal adder: A mixed binary and BCD approach

doi:10.1109/TC.2007.1067

2007-10-01

PRE

Dadda, Luigi *

DOI：10.1109/TC.2007.1067

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摘要

En 中文

Decimal arithmetic has been revived in recent years due to the large amount of data in commercial applications. We consider the problem of Multioperand Parallel Decimal Addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. We adopt the latter approach, which is particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion moreover allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the BD conversion as a design tool.

Keyword:

computer arithmetic

decimal arithmetic

multioperand adders

hardware design