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Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping
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DOI：10.1109/TCSII.2024.3391004.png)
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摘要
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The decomposition of multiplexers (MUXes) implies the representation of n-to-1 MUXes in terms of basic logic gates. This decomposition significantly impacts the performance of the subsequent optimization and matching in technology mapping. In this brief, we propose a network-architecture-aware multiplexer decomposition that decomposes an n-to-1 MUX into one of two significantly distinct architectures. Specially, a delay-evaluation-based guidance scheme estimates the total delay of the two architectures and then selects the optimal architecture for decomposing. Experimental results demonstrate that our algorithm outperforms Yosys and Design Compiler.
Keyword:
Logic synthesis
technology mapping
technology decomposition
multiplexer decomposition
multiplexer
Logic synthesis
technology mapping
technology decomposition
multiplexer decomposition
multiplexer
期刊
I
IF:
4.9
论文数:
8.8K
被引数:
2.5W
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