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Neuromorphic Hardware System for Visual Pattern Recognition With Memristor Array and CMOS Neuron
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DOI：10.1109/TIE.2014.2356439.png)
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This paper presents a neuromorphic system for visual pattern recognition realized in hardware. A new learning rule based on modified spike-timing-dependent plasticity is also presented and implemented with passive synaptic devices. The system includes an artificial photoreceptor, a Pr0.7Ca0.3MnO3-based memristor array, and CMOS neurons. The artificial photoreceptor consisting of a CMOS image sensor and a field-programmable gate array converts an image into spike signals, and the memristor array is used to adjust the synaptic weights between the input and output neurons according to the learning rule. A leaky integrate-and-fire model is used for the output neuron that is built together with the image sensor on a single chip. The system has 30 input neurons that are interconnected to 10 output neurons through 300 memristors. Each input neuron corresponding to a pixel in a 5 x 6 pixel image generates voltage pulses according to the pixel value. The voltage pulses are then weighted and integrated by the memristors and the output neurons, respectively, to be compared with a certain threshold voltage above which an output neuron fires. The system has been successfully demonstrated by training and recognizing number images from 0 to 9.
Keyword:
Complimentary metal-oxide-semiconductor (CMOS) image sensor
leaky integrate-and-fire (I-F) neurons
memristor
neural network
neuromorphic
pattern recognition
spike-timing-dependent plasticity (STDP)
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7.2
论文数:
1.8W
被引数:
9.8W
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