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Nonlinear Asymmetric Parasitic Resistance Extraction of Vertical Pillar-Type FET Using Physics-Informed Artificial Neural Network

delete2026-06-11
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PRE
AI
J
Jaewook Yoo
S
Sojin Jung
S
Soohyun Lim
D
Donghyeon Lee
D
Dongsun Shin
J
Junhui Park
S
Sieun Lee
Y
Yang‐Kyu Choi
H
Hagyoul Bae
DOI:10.1109/led.2026.3701017delete
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Abstract

Abstract

En 中文
In this study, a systematic decomposition of nonlinear asymmetric parasitic resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {par}}\text {)}$ </tex-math></inline-formula> is presented for vertical pillar-type field-effect transistors, a promising architecture for achieving 4F<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. By exploiting the forward mode and reverse mode resistance difference, which inherently cancels contact resistance, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {par}}$ </tex-math></inline-formula> is decomposed into three physically distinct components (bias independent-, drain field dependent-, and gate modulated-resistance). The extraction procedure relies solely on measured current-voltage data without requiring technology computer-aided design calibration (TCAD). To model the gate modulated component as a continuous function across the full bias space, a physics-informed artificial neural-network (PI-ANN) combining a separable parametric baseline with a neural-network correction is developed, ensuring extrapolation stability. The method is validated across pillar diameters from 0.40 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.00~\mu $ </tex-math></inline-formula>m, revealing that the drain field-dependent component dominates across all diameters while the fixed component fraction increases with scaling. This framework provides a practical methodology applicable to compact modeling and design- technology co-optimization (DTCO).
Keywords:
Nonlinear parasitic resistance
physics informed-artificial neural network
vertical pillar-type FET

Journal

IEEE Electron Device Letters cover
IEEE Electron Device Letters
IF:
4.5
Papers:
614
Citations:
2.3W

Organization

J
jeonbuk national university
Scholars:
1.7K
Papers: 767
Citations: 0
K
Korea Advanced Institute of Science and Technology
Scholars:
3.2K
Papers: 1.3K
Citations: 254
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