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One electron-based smallest flexible logic cell

delete2012-10-29
delete16
PRE
AI
S
S. J. Kim *
J
J. J. Lee
H
H. J. Kang
J
Jihun Choi
Y
Yun Seop Yu
Y
Yasuo Takahashi
D
D. G. Hasko
DOI:10.1063/1.4761935delete
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摘要

摘要

En 中文
A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4761935]
Keyword:
MULTIPLE-VALUED LOGIC
SINGLE-ELECTRON
TRANSISTORS
MEMORY
HOLE
DOT

期刊

Applied Physics Letters 封面图
Applied Physics Letters
IF:
3.6
论文数:
10.4W
被引数:
17.8W

机构

Hankyong National University 封面图
Hankyong National University
学者数:
837
论文数: 1.0K
被引数: 759
C
Chungbuk National University
学者数:
8.5K
论文数: 8.0K
被引数: 6.4K
U
University of Cambridge
学者数:
7.7W
论文数: 7.1W
被引数: 13.7W
H
Hokkaido University
学者数:
3.6W
论文数: 2.5W
被引数: 2.6W
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