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Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm
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DOI：10.1109/ACCESS.2020.3016039.png)
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Abstract
En 中文
With the growing complexity of integrated circuits (IC), more and more test patterns are added to test set to test more defects, making the number of test pattern and individual test pattern length continues to increase as the size of IC gets larger, boosting test time and consequently test cost. To solve this problem, this paper proposes a kind of valid pattern identification method. The method uses machine learning to reorder the test pattern which can select the most effective patterns, to determine the optimal training set and test set first. Then, by means of the weighted SVMRANK algorithm to find the optimal pattern sequence. Experiment results demonstrate that the method only sacrifices 2% prediction accuracy in exchange for 3.89 times the time saving. The method aims at maximizing the accuracy of test, and minimizing the number of patterns. The proposed idea significantly improves the test time and test efficiency compared to conventional test flows. This is an innovative test cost reduction method with the growing complexity of IC.
Keywords:
Testing
Integrated circuits
Pressing
Redundancy
Complexity theory
Machine learning
Machine learning algorithms
Adaptive test
machine learning
test reorder
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