arrow
返回

PC-based DTV architecture

delete2000-05-01
delete2
PRE
AI
T
Tran, T *
M
Moriarty, M
D
Dao, G
W
Welker, M
DOI:10.1109/30.846666delete
delete原文链接
delete原文求助
delete分享
delete收藏
摘要

摘要

En 中文
This paper presents the first PC-Based DTV Architecture using an industry standard PCI bus to transfer decoded video data from a DTV decoder to the graphics subsystem of a multimedia PC. The proposed architecture eliminates: 1) the need for a dedicated video port cable between a PC-based DTV decoder and a graphics controller, and 2) the need for a nonstandard graphics controller video port. This paper also presents a novel concept of bursting the decoded DTV data over the PCI bus with no visible video artifacts due to bus latency or different video/graphics refresh rates. In normal operation, this architecture consumes only about 31% of the bandwidth of a 33MHz 32-bit PCI bus.

期刊

IEEE Transactions on Consumer Electronics 封面图
IEEE Transactions on Consumer Electronics
IF:
10.9
论文数:
5.3K
被引数:
6.8K

机构

暂无机构信息
引用论文

引用论文

A single-chip HDTV video decoder design
err1998-08-01
err3
PREAI
errSita, R; Brosz, E; Meyer, R; Phillips, L; Ryan, RT
err分享
err收藏