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ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
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DOI：10.1109/TVLSI.2026.3680055.png)
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Abstract
En 中文
This brief presents a cortical neural pool (CNP) architecture incorporating a high-speed, resource-efficient CORDIC-based Hodgkin–Huxley (RCHH) neuron. The design employs modular CORDIC stages with a latency–area tradeoff and introduces a constraint-aware modular parallelism (CAMP) scheme with precision and stability handling. The FPGA implementation achieves 24.5% lower LUT utilization and 35.2% faster execution than prior designs while reducing normalized root-mean-square error (NRMSE) by 70%. The CNP engine provides <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.85\times $ </tex-math></inline-formula> higher throughput (12.69 GOPS) than a functionally equivalent CORDIC-based DNN accelerator with only 0.35% accuracy degradation on MNIST. These results demonstrate a biologically accurate, resource-efficient cortical neural acceleration engine (NCE) that employs modular CORDIC stages with a latency–area tradeoff, making it suitable for resource-constrained edge-AI systems. The implementation is publicly available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/mukullokhande99/CNP_RCHH</uri>
Keywords:
CORDIC algorithm
FPGA accelerators
Hodgkin–Huxley (H&H) neuron
neuromorphic hardware
spiking neural networks (SNNs)
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