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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
Papers
494
Citations
7349
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Journal Papers
495
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Journal Papers
495
Publication Date
Publication Date
IF
Citations
Collaborative Optimization of High-Order Double Encoding and Differentiated Refresh for RRAM-Based In-Memory Computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-10-12
0
PRE
AI
Debao Wei; Jingyuan Qu; Aiqiang Lei; Yanlong Zeng; Liyan Qiao
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Sparkle: A High-Performance Spatially Fused Event-Driven Accelerator for Spiking Convolutional Neural Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-10-08
0
PRE
AI
Tengxiao Wang; Junfeng You; Jialin Yang; Ying Jiang; Yingcheng Lin; Junxian He; Zhengqing Zhong; Liyuan Liu; Cong Shi
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A 28-nm Sparse Transformer Accelerator With Row-Wise Run-Length Compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-10-08
0
PRE
AI
Yuan Liao; Jian Meng; Jae-sun Seo
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A High-Throughput Stereo Matching Accelerator for Resource-Constrained FPGAs via Algorithm-Hardware Co-Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-10-08
0
PRE
AI
Guanyu Zhang; Ying Ren; Jiawei Feng; Yang Liu
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A Speculative Trellis Decoder for Lossless LLM Weight Decompression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-10-08
0
PRE
AI
Injae Yoo
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SAFT: Mitigating DRAM Faults in PIM-Based LLM Inference via Sensitivity-Aware Fine-Tuning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-10-08
0
PRE
AI
Yang Wang; Qi Xu; Song Chen; Yi Kang
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An Efficient XOR-TERO PUF Based on Duty-Cycle Truncation for Stable Key Generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-10-08
0
PRE
AI
Zhengfeng Huang; Zezheng Wang; Jie Li; Yingchun Lu; Jingchang Bian; Yankun Lin; Zhao Yang; Tianming Ni; Xiaoqing Wen
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SATurbine: A Multicore Transformer Accelerator With Gated Broadcast for Efficient Dynamic Sparse Attention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-09-25
0
PRE
AI
Wentao Xu; Yuxuan Zhang; Rongzhou Zhu; Xiang Wu; Zehao Wang; Weilin Li; Jiaxiang Wang; Chunyang Du; Yuanlu Gao; Zhanxiang Gao; Fengdong Qu; Jinming Lu; Li Du
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Performance Is the Sole Target: Power Budgeting Assisted Thermal-Aware Processor Floorplanning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-09-22
0
PRE
AI
Hai Wang; Zhijie Zhang; Changyi Qin
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A 94.3%-Efficient Battery-Less BLE Sensor Node SoC With a −0.5 °C to +1 °C Room-Temperature Two-Point Calibrated Temperature Sensor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-09-17
0
PRE
AI
Ju-Won Oh; Sung-Jae Lee; Sung-Gyu Kim; Jong Wan Jo; Yeonjae Jung; Young-Gun Pu; Kang-Yoon Lee; Jun-Eun Park
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TREA: Low-Precision Time-Multiplexed, Resource-Efficient Edge Accelerator for Object Detection and Classification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-09-15
0
PRE
AI
Vijay Pratap Sharma; Mukul Lokhande; Ratko Pilipović; Omkar Kokane; Santosh Kumar Vishvakarma
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An NRZ/PAM-4 Dual-Mode Transmitter Using Tx-Interleaving Technique for Low-Power DRAM Interfaces
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-09-14
0
PRE
AI
Hang-Min Jo; Young-Min Lee; Jun-Sung Kim; Won-Young Lee
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Unifying Feed-Forward and Weight-Gradient: An Energy-Efficient Architecture for On-Chip SNN Learning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-09-09
0
PRE
AI
Yue Zuo; Ning Ning; Zhiao Su; Zhilin Li; Shengxin Wang; Chengwang Wu; Zhiwei You; Guanchao Qiao; Yang Liu; Shaogang Hu
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A Robust Radar Accelerator for Continuous Fall Detection via Centroid-Guided Activation and Groupwise Quantized Spatio-Temporal CNN
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-09-09
0
PRE
AI
Zuo Zhang; Yunqi Guan; Linxin Yang; Wenbin Ye
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A 2D-DCT Processor Using One-Time-Programmed Floating-Gate Transistor Array for Processing-in-Sensor Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-08-26
0
PRE
AI
Junjie Shen; Ye Lin; Wei Jiang; Dawei Li; Yuan Du; Li Du; Jingjing Lv
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A Low-Cost Wireless Remote Debugging Architecture for AMD/Xilinx FPGA Families
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-08-20
0
PRE
AI
Mohamed A. Elshiemy; Ahmed I. Ahmed; Samy H. Sharf; Ahmed Soltan; Ahmed H. Madian; Inês Gouveia; Ali Shoker
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High-Throughput and Area-Efficient Parallel Multimode BCH Encoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-08-18
0
PRE
AI
Hansol Jeong; Jeongmin Kim; Jaehoon Kwon; In-Cheol Park
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An Energy-Efficient, Low-Complexity Parallel Stochastic Multiplier Using Partial Products
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-08-18
0
PRE
AI
Yudi Zhao; Qiang He; Zhihuai Zhang; Xiaofei Nie; Ye Lu; Shisheng Xiong; Kai Zhao
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Backside Signal Intracell Routing Beyond Backside Power Delivery for Angstrom Nodes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-08-17
0
PRE
AI
Junjong Lee; Dae-Hwan Kim; Sung-Jin Choi; Yoon Jung Lee
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SPACE: Safety-Critical Performance-Counter Adaptive Control Engine for Anomaly Mitigation via Deep Reinforcement Learning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-08-17
0
PRE
AI
Elio Vinciguerra; Nooshin Nosrati; Giuseppe Ascia; Maurizio Palesi; Ahmed Hemani
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