Canyam
AI summaries for academic research
Home
Preprint
Subscribe
Favorites
Tools
Analysis
Summary
Not logged in
Back
Journal Details
I
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
Papers
424
Citations
7349
Related Insights
0
subscribe
Journal Papers
425
Related Insights
0
Journal Papers
425
Publication Date
Publication Date
IF
Citations
An Efficient Hardware Accelerator for CKKS En/Decoding and En/Decryption With Dynamic Twiddle Factor Generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-06-08
0
PRE
AI
Pengfei Sun; Makoto Ikeda
Share
Save
Polar Code With Parity Check-Assisted Pruning for Error Correction in Modern Flash Memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-06-05
0
PRE
AI
Debao Wei; Huqi Xiang; Yongchao Wang; Zhelong Piao; Liyan Qiao
Share
Save
Design of Random Forest-Based Low-Power VLSI Architecture to Detect Congestive Heart Failure for Wearable Devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-06-04
0
PRE
AI
Abhyuday Bhardwaj; Meenali Janveja; Srinivasan Krishnaswamy; Jan Pidanic; Gaurav Trivedi
Share
Save
HardVault: A Hybrid FPGA-Based Ethereum-Bitcoin Cold Wallet
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-06-01
0
OA
AI
Joel Poncha Lemayian; Ghyslain Gagnon; Kaiwen Zhang; Pascal Giard
Share
Save
A Novel Unified Newton Structure-Based Fractional Delay Filter for Low-Complexity Reconfigurable Arbitrary Bandwidth Filters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-26
0
PRE
AI
T. C. Jayasree; S. Shaeen Kalathil; R. Nandakumar; T. Bindima
Share
Save
TQ-SPUF: A Software PUF Design Based on HEVC Transform and Quantization Module for Device Security and Video Anti-Tampering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-19
0
PRE
AI
Kejie Wang; Yuejun Zhang; Shuang Hu; Ziyu Zhou; Zhenkai Zhou; Huihong Zhang; Pengjun Wang
Share
Save
Identifying Failing Flip-Flops in Scan-Based Designs Using Highly Compressed Test Results
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-14
0
PRE
AI
Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer
Share
Save
An Energy-Efficient Block-Convolution-Based Super-Resolution Processor With Tiling Artifact Reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-12
0
PRE
AI
Byeungseok Yoo; Sungjin Park; Sunwoo Lee; Dongsuk Jeon
Share
Save
Analysis and Validation of Duty-Cycle-Based MPPT for Piezoelectric Energy Harvesting: Impact of Nonideal Losses on Optimal Duty Cycle
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-12
0
PRE
AI
Xiudeng Wang; Shulin Gao; Libo Qian; Yongyuan Li; Zhangming Zhu
Share
Save
RAW-PM: Reliability-Aware Weighted Polar Mapping for Hard-Decision Decoding in 3-D NAND Flash Memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-11
0
PRE
AI
Debao Wei; Huqi Xiang; Dixin Ma; Yongchao Wang; Liyan Qiao
Share
Save
Low-Complexity Parallel Syndrome Computation and Chien Search Architecture Based on Reed--Muller Transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-11
0
PRE
AI
Muxun Zhang; Suwen Song; Liyang Zhou
Share
Save
A Groupwise Add--Multiply--Shift--Accumulate Datapath for Efficient DNN Accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-08
0
PRE
AI
Zhiwang Huo; Wenzhe Zhao; Yuanchang Gong; Tian Xia; Zheng Wang; Pengju Ren
Share
Save
A Low-Power, High-Throughput Multimode FFT Processor Incorporating the ASPC Algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-08
0
PRE
AI
Kuang-Hao Lin; Tzu-Yi Tseng
Share
Save
High-Performance FPGA-Based LZ77 Accelerator Design With Deep-Search Capability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-08
0
PRE
AI
Hao Xiao; Han Xu; Yu Ren; Saiqin Xu
Share
Save
A Bit-Level Loosely Coupled Spiking Neural Network Accelerator With Fast Inference and Hybrid Early Termination
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-07
0
PRE
AI
Junchuan Gu; Yiwen Gu; Xinran Li; Haibin Shen; Kejie Huang
Share
Save
TriCIM: A General CIM-Capacity-Aware Framework for Optimizing Model, Layer, and Tile-Stationary Dataflows in CIM Accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-07
0
PRE
AI
Jin Wang; Yufu Zhang; Longyang Lin
Share
Save
Topology Optimization of 3-D NoC for High-Speed Data Acquisition Systems via Deep Reinforcement Learning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-07
0
PRE
AI
Yunhui Deng; Chuanpei Xu; Wei Mo; Chunting Wan
Share
Save
Energy-Efficient Logarithmic Floating-Point Multipliers Using Truncation-Based Error Compensation for Fault-Tolerant Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-05
0
PRE
AI
Zheng Li; Baining Wu; Jilong Zhang; Chao Chen; Yongliang Zhang; Yan Li; Xiaoyang Zeng
Share
Save
Algorithm--Hardware Co-Design of Digital Compute-in-Memory Architecture Supporting Flexible and Temporal N:M Sparsity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-05
0
PRE
AI
Akshat Ramachandran; Souvik Kundu; Arnab Raha; Shamik Kundu; Deepak A. Mathaikutty; Tushar Krishna
Share
Save
FANE: FPGA-Based FP8 Approximate Neural Network Engine
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF
3.1
2026-05-04
0
PRE
AI
Han Bao; Shidi Tang; Jingdong Li; Ahmed Sadaqa; Ruiqi Chen; Ming Ling; Bruno da Silva
Share
Save
.png){kind=icon}
.png){kind=icon}
Not logged in.png){kind=icon}
Not logged in.png){kind=icon}
.png){kind=icon}
.png){kind=icon}
.png){kind=icon}
