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SiC MOSFET threshold-stability issues
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DOI：10.1016/j.mssp.2017.11.028.png)
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Abstract
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This work provides additional insight into the threshold-voltage instability effect generally observed, to varying degrees, in SiC MOSFETs, and discusses the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold-voltage stability is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence of the direct-tunneling mechanism in response to changes in gate bias. Bias-temperature stressing can induce additional active oxide traps that can then participate in this instability. This time dependence is not properly accounted for in the existing test methods for assessing high-temperature gate-bias (HTGB) effects.
Keywords:
SiC
MOSFET
Semiconductor device reliability
Threshold voltage
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