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4-bit CNN Quantization Method With Compact LUT-Based Multiplier Implementation on FPGA
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DOI：10.1109/TIM.2023.3324357.png)
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Abstract
En 中文
To address the challenge of deploying convolutional neural networks (CNNs) on edge devices with limited resources, this article presents an effective 4-bit quantization scheme for CNN and proposes a DSP-free multiplier solution for deploying quantized neural networks on field-programmable gate array (FPGA) devices. Specifically, we first introduce a threshold-aware quantization (TAQ) method with a mixed rounding strategy to compress the scale of the model while maintaining the accuracy of the original full-precision model. Experimental results demonstrate that the proposed quantization method retains a high classification accuracy for 4-bit quantized CNN models. In addition, we propose a compact lookup table-based multiplier (CLM) design that replaces numerical multiplication with a lookup table (LUT) of precomputed 4-bit multiplication results, leveraging LUT6 resources instead of scarce DSP blocks to improve the scalability of FPGA to implement multiplication-intensive CNN algorithms. The proposed 4-bit CLM only consumes 13 LUT6 resources, surpassing the existing LUT-based multipliers (LMULs) in terms of resource consumption. The proposed CNN quantization and CLM multiplier scheme effectively save FPGA resource consumption for FPGA implementation on image classification tasks, providing strong support for deep learning algorithms in unmanned systems, industrial inspection, and other relevant vision and measurement scenarios running on DSP-constrained edge devices.
Keywords:
Quantization (signal)
Field programmable gate arrays
Convolutional neural networks
Hardware
Convolution
Complexity theory
Power demand
Convolutional neural network (CNN)
digital circuit
field-programmable gate array (FPGA)
lookup table (LUT)-based multiplier
low-precision quantization
Journal
IF:
5.9
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1.9W
Citations:
5.8W