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A BFS-Based DEVS Simulation Kernel for HDL-Compatible Simulation
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DOI：10.3390/electronics15010048.png)
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Abstract
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The Discrete Event System Specification (DEVS) formalism provides a mathematical foundation for modeling hierarchical discrete-event systems. However, the Depth-First Search (DFS) scheduling used in the classical DEVS abstract simulator conflicts with the concurrency semantics of Hardware Description Language (HDL) simulators such as Verilog or VHDL. This mismatch induces timing distortions, including pipeline skew and zero-time feedback loops. To address these limitations, this study proposes a new DEVS simulation kernel that adopts Breadth-First Search (BFS) scheduling, integrating the delta-round concept. This approach employs an event-parking mechanism that separates event computation from application, structurally aligning with HDL’s Active–NBA–Reactive phases and enabling semantically simultaneous updates without introducing additional ε-time. Case studies demonstrate that the proposed BFS-based DEVS kernel eliminates timing discrepancies in pipeline and feedback-loop structures and establishes a formal foundation for semantic alignment between DEVS and HDL simulators.
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