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A Current-Based Write Method for Multibit IGZO 2T0C DRAM
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DOI：10.1109/TED.2026.3669474.png)
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Abstract
En 中文
We propose a novel current-based write method in IGZO 2T0C DRAM that compensates threshold voltage (V-TH) variations. During the write operation, current is written to 2T0C cells via the common bitline (BL), generating a self-calibrated storage node (SN) voltage (V-SN) corresponding to distinct current values. Different cells programmed with the same current value then generate identical overdrive voltages (V-SN-V-TH) on the read transistors, resulting in highly uniform read currents independent of V-TH variations. By this design, 4-bit storage among 25 IGZO 2T0C cells is achieved. This work paves a new path toward multibit DRAM applications.
Keywords:
Random access memory
Transistors
Threshold voltage
Programming
Logic gates
Fabrication
Timing
Scanning electron microscopy
Fluctuations
Temperature
array
IGZO
multibit
VTH compensation
Journal
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3.2
Papers:
685
Citations:
3.7W