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A Current-Steering DAC With a Complementary Structured Charge-Pump-Based Voltage-Limited Driver for Code-Dependent Error Suppression
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DOI：10.1109/TVLSI.2026.3685243.png)
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Abstract
En 中文
This brief presents a voltage-limited driver based on a complementary structured charge-pump (CSCP) for current-steering digital-to-analog converters (CS-DACs), which is compatible with the complementary structured latch architecture. The proposed driver limits the voltage swing to prevent overvoltage stress on the current-source switches. The complementary architecture eliminates code-dependent disturbances introduced by charge-pump switching activity. A 12-bit 100-MS/s DAC incorporating the proposed CSCP driver was fabricated in a 55-nm CMOS process and occupies an active area of 1.17 mm2. The DAC operates with a 1.8-V analog supply and a 1.2-V digital supply, dissipating 29.1 mW. Measurement results show a spurious-free dynamic range (SFDR) of up to 80.42 dBc when dynamic element matching (DEM) is applied. The differential nonlinearity (DNL) and integral nonlinearity (INL) are within ±0.33 and ±0.62 least significant bit (LSB), respectively.
Keywords:
Charge-pump
code-dependent error
current-steering
digital-to-analog converter (DAC)
voltage-limited current switch driver circuit
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440
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