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A Hardware-Efficient Large-Kernel Convolution-Based Super-Resolution Accelerator
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DOI：10.1109/tcsi.2026.3732539.png)
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Abstract
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Large-kernel convolutional networks have enabled CNN-based image super-resolution (SR) methods to achieve encouraging reconstruction quality. However, the large-kernel design poses severe challenges in computational throughput and energy consumption, hindering their deployment on edge devices. Given this, a high-throughput and energy-efficient SR accelerator for large-kernel convolution-based SR models is proposed. For hardware-efficient large-kernel algorithm design, we combine “multiplication-free” shift operations with a kernel decomposition strategy to simplify large-kernel convolutions and fundamentally shrink the computation load. For efficient shift large-kernel computation acceleration, we design a vector-line-buffer-based shift large-kernel convolution unit to cache feature rows on-chip and generate shifted vectors locally, while simultaneously performing multi-directional shifting, thereby reducing the latency of the shift large-kernel convolution. For computation-intensive pointwise convolution, we present a clustered systolic cube architecture that decomposes a monolithic systolic array into parallel cubelets to shorten the data propagation path and groups the array into clusters to improve PE utilization, leading to higher throughput and better energy efficiency. Extensive prototyping demonstrates that our presented accelerator achieves a record-high throughput of up to 1009 Mpixels/s on FPGA and an energy efficiency of 2093 Mpixels/J on ASIC, which is over $1.58\times $ and $1.95\times $ higher than recent state-of-the-art works.
Keywords:
Convolutional neural network (CNN)
field-programmable gate array (FPGA)
super-resolution
image processing
edge computing
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