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A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference

delete2025-07-01
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PRE
AI
J
Jinkai Wang
Y
Youxiang Chen
Z
Zekun Wang
Z
Zhengkun Gu
B
Bojun Zhang
H
Haiming Qiu
K
Kun Zhang
W
Weisheng Zhao
张
张跃 (Yue Zhang)
DOI:10.1109/TCSI.2025.3543104delete
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Abstract

Abstract

En 中文
Computing in memory (CIM) is one of the promising solutions to improve computing performance by integrating logic in memory. This work presents an efficient heterogeneous system based on the ultrafast CIM architecture (HS-CIM) to accelerate convolutional neural network (CNN) inference. First, an ultrafast CIM architecture is proposed based on the static random access memory (SRAM) by utilizing the novel total input and full digital scheme to implement multiply-and-accumulate (MAC) operation, which effectively addresses the high delay issue caused by high-precision computing in CIM architecture. Second, a heterogeneous system based on the proposed CIM architecture (HS-CIM) has been constructed with an aligned global cache and an adaptive pruning scheme to eliminate performance degradation and accuracy loss caused by input data bandwidth limitations. Meanwhile, efficient input data and weight data mapping schemes are proposed to minimize the delay and energy caused by input data transmission from the cache to the CIM architecture, thus realizing efficient CNN inference in the HS-CIM system. Finally, we analyze the performance of HS-CIM at the layout level by implementing the LeNet-5 and VGG models of CNN to recognize the image of MNIST and CIFAR-10 datasets, respectively. Results show that the energy efficiency of the proposed CIM architecture achieves 58.32 TOPS/W with 8-bit input/weight precision. Meanwhile, the inference accuracy of the HS-CIM system for MNIST and CIFAR-10 is 99.25% and 92.34%, respectively.
Keywords:
Computing in memory (CIM)
heterogeneous system
SRAM
CNN

Journal

IEEE Transactions on Circuits and Systems I-Regular Papers cover
IEEE Transactions on Circuits and Systems I-Regular Papers
IF:
5.2
Papers:
9.8K
Citations:
2.2W

Organization

B
Beihang University
Scholars:
5.2W
Papers: 4.1W
Citations: 37
Cited Papers

Cited Papers

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
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8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices
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Rethinking the Inception Architecture for Computer Vision
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A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips
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16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices
err2021-02-13
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errCheng-Xin Xue; Je-Min Hung; Hui-Yao Kao; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Peng Chen; Ta-Wei Liu; Chuan-Jia Jhang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; Tsung-Yung Jonathan Chang; Meng-Fan Chang
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Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing
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errHongyang Jia; Murat Ozatay; Yinqi Tang; Hossein Valavi; Rakshit Pathak; Jinseok Lee; Naveen Verma
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A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips
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errXin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Nan-Chun Lien; Wei-Chiang Shih; Yajuan He; Qiang Li; Meng-Fan Chang
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