A Novel RFET-Based FPGA Architecture Based on Delay-Aware Packing Algorithm

doi:10.1109/TETC.2025.3572712

A Novel RFET-Based FPGA Architecture Based on Delay-Aware Packing Algorithm

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DOI：10.1109/TETC.2025.3572712

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Reconfigurable devices are attracting growing interest as both a potential alternative and complement to traditional CMOS technology. This paper develops a novel field-programmable gate array (FPGA) architecture based on MClusters, which is made of fast and area-efficient 2-input look-up tables (LUTs) through reconfigurable field-effect transistors (RFETs). To fully utilize the MClusters, we propose an SAT-based delay-aware packing algorithm for the technology mapping. In addition, we integrate a partitioning algorithm to divide the circuit into several sub-circuits to further reduce the global routing resources and their associated switching energy of the system. Finally, we develop an efficient technology/circuit/system co-design framework for optimizing the overall performance of FPGAs. Based on comprehensive benchmarking, results demonstrate that optimal design yields significant reductions of up to 39% area, 36% wire length, and 40% switching energy compared to traditional CMOS 6-input LUT FPGAs.

Keywords:

Reconfigurable FET

field-programmable gate arrays

look-up table

circuit partitioning

packing algorithm

technology mapping

PSO

performance benchmarking

A Novel RFET-Based FPGA Architecture Based on Delay-Aware Packing Algorithm

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