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A RISC-V Accelerator for Sequence Decoding in Mobile DNA Sequencers
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DOI：10.1109/TVLSI.2025.3639548.png)
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Abstract
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Modern nanopore sequencers generate raw signal data at high speed, demanding low-latency and energy-efficient basecalling pipelines to enable fully portable genomic analysis. In this work, we present a hardware accelerator for the Viterbi-based connectionist temporal classification (CTC) decoding stage of basecalling—a key bottleneck in translating neural network outputs into deoxyribonucleic acid (DNA) sequences. Our design is the first pipelined CTC Viterbi decoder architecture tailored for nanopore sequencing and is implemented on a Xilinx Virtex-7 (VC707) FPGA within a Linux-capable reduced instruction set computer-fifth generation (RISC-V) system-on-chip (SoC). The accelerator processes over 23 000 DNA bases per second at 100 MHz with about $4.3~\boldsymbol {\mu }$ s per-sample latency and only 0.43-W overhead power. This corresponds to $\textbf {5.3}\times \mathbf {10^{4}}$ bases/J ( $19~\boldsymbol {\mu }$ J/base) and yields approximately 7x end-to-end speedup over a CPU baseline, while reserving the baseline read-identity accuracy. For the same CTC task, the accelerator delivers 29x higher throughput than a recent FPGA beam-search decoder. These results demonstrate the viability of dedicated decoding accelerators for real time, on-device genomic processing in power-constrained environments.
Keywords:
Connectionist temporal classification (CTC) decoder
deoxyribonucleic acid (DNA) sequencing
machine learning
reduced instruction set computer-fifth generation (RISC-V)
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440
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