An Error Correction Code-Based Self-Test for Buffer-Die in High-Bandwidth Memory

Seonghun Jang

doi:10.1109/tcsi.2026.3730160

An Error Correction Code-Based Self-Test for Buffer-Die in High-Bandwidth Memory

2026-09-11

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DOI：10.1109/tcsi.2026.3730160

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As high-bandwidth memory (HBM) performance continues to increase, buffer-die logic integrates increasingly diverse control, reliability, and test functions within a limited area budget. Therefore, reducing the hardware overhead of test-support logic is an important design consideration. Conventional logic built-in self-test (LBIST) uses standalone pseudo-random pattern generator (PRPG) and multiple-input signature register (MISR) blocks for pattern generation and response compaction, adding dedicated test hardware. This article proposes a self-test architecture for buffer-die in HBM based on error correction code (ECC) reuse. In particular, by exploiting the fact that the native system ECC (S-ECC) in HBM operates through cyclic redundancy check (CRC), the S-ECC is repurposed as the PRPG and MISR. A pre-test verification procedure is also introduced to validate the reused ECC before it is used as an on-chip test resource. Experimental results show that the proposed serial and parallel S-ECCs achieve 5.6% and 4.23% reductions in test-support hardware area, respectively, while maintaining comparable test effectiveness and test cost compared with conventional LBIST. These results demonstrate that S-ECC reuse provides an area-efficient LBIST architecture for HBM3 buffer-die logic while maintaining comparable test capability and test cost.

Keywords:

High-bandwidth memory (HBM)

logic built-in self-test (LBIST)

pseudo-random pattern generator (PRPG)

multiple-input signature register (MISR)

error-correction code (ECC)

An Error Correction Code-Based Self-Test for Buffer-Die in High-Bandwidth Memory

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