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Big Integer Parallel Stream Modular Multiplier With Variable Bit-Widths
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DOI：10.1109/TCAD.2025.3584844.png)
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Abstract
En 中文
In this article, we present a new modular multiplier design that offers flexibility regarding the operand sizes it processes in parallel. The multiplier can efficiently compute different sizes using the same ASIC hardware, enabling parallel computations for smaller sizes, for example a 1024-bit instantiation of our multiplier can perform either one 1024-bit, sixteen 64-bit, or four 256-bit multiplications, etc. This capability is particularly valuable in accelerating a plethora of cryptosystems, such as RSA, ECC, or fully homomorphic encryption (FHE), using the same ASIC hardware, since operand sizes can vary depending on the security parameters and the application requirements. The multiplier can be used in conjunction with software methods for parallelization. For instance, our multiplier enables users to employ both residue number system (RNS) and non-RNS versions of FHE using a single hardware accelerator. We implement our multiplier in hardware and demonstrate its efficiency compared to state-of-the-art Montgomery designs, while offering the additional advantage of parallel processing flexibility.
Keywords:
Hardware
Arithmetic
Cryptography
Software
Runtime
Computational efficiency
Training
Throughput
Homomorphic encryption
Hardware acceleration
Digital arithmetic
digital circuits
hardware acceleration
homomorphic encryption
parallel architectures
Journal
I
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2.9
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606
Citations:
9.6K
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