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Chipletizer 2.0: Toward Cost-Effective Chiplet Design via Reuse-Aware Decomposition
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DOI：10.1109/TCAD.2025.3602743.png)
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Abstract
En 中文
The decomposition-based chiplet design paradigm, which breaks monolithic system-on-chips (SoCs) into smaller chiplets, has proved effective in reducing costs and accelerating development. The vast design space of multichiplet systems necessitates automated techniques to maximize their benefits while minimizing overheads. However, current chiplet decomposition flows lack support for exploring reusable chiplets, missing opportunities to efficiently amortize nonrecurring engineering (NRE) costs. To fully unleash the economic potential of chiplets, we propose Chipletizer 2.0, a cost-driven framework that guides SoC decomposition and enables chiplet reuse across a line of products. This early-stage chiplet planning framework determines critical system parameters involving the partition, floorplan, and die-to-die (D2D) interface, based on user-specified optimization goals. Experimental results demonstrate that, compared with the existing chiplet decomposition techniques, our proposed framework achieves significant cost improvements on realistic product lines with acceptable overheads.
Keywords:
Chiplets
Costs
Device-to-device communication
IP networks
Hardware
Program processors
Planning
Computers
Substrates
Optimization
Chiplet
chiplet floorplanning
design partitioning
die-to-die (D2D) interface
system-on-chip (SoC)
Journal
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2.9
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564
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9.6K
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Cited Papers