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Circuits to Systems: Codesigning Efficient AI Hardware

delete2025-12-01
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PRE
AI
Y
Yiran Chen *
C
Cong Guo
Y
Yintao He
M
Mingyuan Ma
T
Tergel Molom-Ochir
N
Nicky Ramos
H
Haoxuan Shan
W
Wei, Chiyue
李海 cover
李海 (Hai Li)
DOI:10.1109/MDAT.2025.3600328delete
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Abstract

Abstract

En 中文
Editor's notes: The authors explore the intertwined progress of circuit innovation and system architecture that has propelled AI development-from early neuro-morphic circuits to today's memory-centric accelerators. They review milestones such as processing-in-memory, GPUs, and systolic arrays and address emerging challenges from large language models. -Jorg Henkel, Vice-President of Publications, IEEE CEDA -L. Miguel Silveira, President, IEEE CEDA
Keywords:
Artificial intelligence
Hardware
Computer architecture
Graphics processing units
Quantization (signal)
Training
Systolic arrays
Deep learning
Computational modeling
Architecture
Circuit synthesis
Circuits
Systems
Co-design
Neuromorphic Computing
AI Acceleration
Large Language Models

Journal

I
IEEE Design & Test
IF:
1.9
Papers:
39
Citations:
0

Organization

D
duke university
Scholars:
8.5K
Papers: 3.4K
Citations: 2
Cited Papers

Cited Papers

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Efficient Memory Management for Large Language Model Serving with PagedAttention
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Dot-product engine for neuromorphic computing
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Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network
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errHardik Sharma; Jongse Park; Naveen Suda; Liangzhen Lai; Benson Chau; Joon Kyung Kim; Vikas Chandra; Hadi Esmaeilzadeh
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Differentiable Content Addressable Memory with Memristors
err2022-03-02
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