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CodeV: Empowering LLMs With HDL Generation Through Multilevel Summarization
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DOI：10.1109/TCAD.2025.3604320.png)
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Abstract
En 中文
The design flow of processors, particularly in hardware description languages (HDLs) like Verilog and Chisel, is complex and costly. While recent advances in large language models (LLMs) have significantly improved coding tasks in software languages such as Python, their application in HDL generation remains limited due to the scarcity of high-quality HDL data. Traditional methods of adapting LLMs for hardware design rely on synthetic HDL datasets, which often suffer from low quality because even advanced LLMs like GPT perform poorly in the HDL domain. Moreover, these methods focus solely on chat tasks and the Verilog language, limiting their application scenarios. In this article, we observe that: 1) HDL code collected from the real world is of higher quality than that generated by LLMs; 2) LLMs like GPT-3.5 excel in summarizing HDL code rather than generating it; and 3) an explicit language tag can help LLMs better adapt to the target language when there is insufficient data. Based on these observations, we propose an efficient LLM fine-tuning pipeline for HDL generation that integrates a multilevel summarization (MLS) data synthesis process with a novel Chat-FIM-Tag supervised fine-tuning method. The pipeline enhances the generation of HDL code from natural language descriptions and enables the handling of various tasks, such as chat and infilling incomplete code. Utilizing this pipeline, we introduce CodeV, a series of HDL generation LLMs. Among them, CodeV-All not only possesses a more diverse range of language abilities (Verilog and Chisel) and a broader scope of tasks (Chat and FIM), but also achieves performance on VerilogEval that is comparable to that of CodeV-Verilog fine-tuned on Verilog only, making them the first series of open-source LLMs designed for multiscenario HDL generation. The code, models, and dataset are available at https://github.com/IPRC-DIP/CodeV
Keywords:
Hardware design languages
Codes
Benchmark testing
Pipelines
Program processors
Training
Software
Python
Hardware
Encoding
Hardware design language (HDL) generation
large language models (LLMs)
processor design automation
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