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Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures
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DOI：10.1109/TCSII.2020.3038462.png)
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Abstract
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This brief introduces a new method to compute in parallel the roots of a polynomial locator of degree four in a Reed-Solomon decoder. The novelty of this brief is the introduction of an algorithm that transforms the polynomial locator obtained with the Peterson-Gorenstein-Zierler's algorithm into an equivalent one that allows a direct search for the four roots that indicate the location of the symbols in error. This new solution improves a previous approach proposed in the literature for a quadruple-error-correction decoder (QEC) that requires a cubic aid equation. This previous solution does not work in the cases in which the cubic aid does not have a solution. In contrast, the proposal of this brief works in 100% of cases (with t <= 4) as it solves an equivalent polynomial. This new algorithm allows two different implementations: a fully parallel architecture which provides an extremely low latency at an extra area cost, and a fully serial architecture with less area, but a higher latency.
Keywords:
Decoding
Computer architecture
Hardware
Mathematical model
Circuits and systems
Reed-Solomon codes
Proposals
Error correction
Reed-Solomon codes
memory protection
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