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J
Juan Antonio Maestro
complutense university of madrid
31
H-index
209
Paper Count
3.3K
Citation Count
0
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Published Papers
50
Publication Date
Publication Date
Impact Factor
Citations
Low-Complexity Syndrome-Based Linear Programming Decoding of Quantum LDPC Codes
IEEE Transactions on Quantum Engineering
IF
4.6
2026-01-01
0
PRE
AI
Javed, Sana; Colet, Sergio; Garcia-Herrero, Francisco; Ruano, Oscar; Maestro, Juan Antonio; Vasic, Bane; Flanagan, Mark F.
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Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications
IEEE TRANSACTIONS ON COMPUTERS
IF
3.8
2025-03-01
0
OA
AI
Bascones, Daniel; Garcia-Herrero, Francisco; Ruano, Oscar; Gonzalez, Carlos; Mozos, Daniel; Maestro, Juan Antonio
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A new radiation-hardened architecture for holographic memory address calculation
ALEXANDRIA ENGINEERING JOURNAL
IF
6.8
2022-08-01
0
OA
AI
Garcia-Herrero, Francisco; Rodriguez-Soriano, Laura; Ruano, Oscar; Maestro, Juan Antonio
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Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors
COMPUTERS & ELECTRICAL ENGINEERING
IF
4.9
2022-04-01
5
PRE
AI
Kuo, Yao-Ming; Garcia-Herrero, Francisco; Ruano, Oscar; Antonio Maestro, Juan
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ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2022-03-01
3
PRE
AI
Alberto Aranda, Luis; Ruano, Oscar; Garcia-Herrero, Francisco; Antonio Maestro, Juan
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RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography
IEEE TRANSACTIONS ON COMPUTERS
IF
3.8
2022-01-01
13
PRE
AI
Kuo, Yao-Ming; Garcia-Herrero, Francisco; Ruano, Oscar; Maestro, Juan Antonio
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Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
IF
5.4
2021-10-01
1
PRE
AI
Garcia-Herrero, Francisco; Sanchez-Macian, Alfonso; Maestro, Juan Antonio
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Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2021-04-01
1
PRE
AI
Garcia-Herrero, Francisco; McGuire, Gary; Flanagan, Mark F.; Sanchez-Macian, Alfonso; Maestro, Juan Antonio
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Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial
SENSORS
IF
3.5
2021-02-17
6
OA
AI
Ruano, Oscar; Garcia-Herrero, Francisco; Aranda, Luis Alberto; Sanchez-Macian, Alfonso; Rodriguez, Laura; Maestro, Juan Antonio
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Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs
IEEE ACCESS
IF
3.6
2021-01-01
2
OA
AI
Aranda, Luis Alberto; Ruano, Oscar; Garcia-Herrero, Francisco; Maestro, Juan Antonio
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Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
IF
5.4
2021-01-01
4
OA
AI
Sanchez-Macian, Alfonso; Martin-Toledano, Alonso; Andres Bravo-Montes, Jefferson; Garcia-Herrero, Francisco; Antonio Maestro, Juan
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Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2020-12-01
0
PRE
AI
Garcia-Herrero, Francisco; Sanchez-Macian, Alfonso; Maestro, Juan Antonio
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Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications
IEEE ACCESS
IF
3.6
2020-01-01
7
OA
AI
Alberto Aranda, Luis; Garcia-Herrero, Francisco; Esteban, Luis; Sanchez-Macian, Alfonso; Antonio Maestro, Juan
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An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs
IEEE TRANSACTIONS ON COMPUTERS
IF
3.8
2019-09-01
23
PRE
AI
Ramos, Alexis; Toral, Ricardo G.; Reviriego, Pedro; Antonio Maestro, Juan
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ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs
IEEE ACCESS
IF
3.6
2019-01-01
26
OA
AI
Alberto Aranda, Luis; Sanchez-Macian, Alfonso; Antonio Maestro, Juan
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A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs
IEEE TRANSACTIONS ON COMPUTERS
IF
3.8
2018-07-01
12
PRE
AI
Gonzalez-Toral, Ricardo; Reviriego, Pedro; Antonio Maestro, Juan; Gao, Zhen
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Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2018-04-01
2
PRE
AI
Gonzalez-Toral, Ricardo; Liu, Shanshan; Reviriego, Pedro; Antonio Maestro, Juan
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Efficient Fault-Tolerant Design for Parallel Matched Filters
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2018-03-01
8
PRE
AI
Gao, Zhen; Zhou, Ming; Reviriego, Pedro; Antonio Maestro, Juan
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A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2018-03-01
10
PRE
AI
Alberto Aranda, Luis; Reviriego, Pedro; Antonio Maestro, Juan
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Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs
IEEE TRANSACTIONS ON COMPUTERS
IF
3.8
2018-02-01
17
PRE
AI
Ramos, Alexis; Ullah, Anees; Reviriego, Pedro; Maestro, Juan Antonio
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Research Directions
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Co-authors
Cooperation Journals
高镇
(Zhen Gao)
H-index: 42 · Papers: 328
B
Bane Vasić
H-index: 42 · Papers: 427
K
Ken Christensen
H-index: 39 · Papers: 249
赵
赵明
(Ming Zhao)
H-index: 39 · Papers: 380
P
Pedro Reviriego
H-index: 33 · Papers: 454
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