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Dynamic binary translation and optimization
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DOI：10.1109/12.931892.png)
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Abstract
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We describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach offers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime profile information to optimize translations so as to extract instruction level parallelism. This work reports different design trade-offs in the DAISY system and their impact on final system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage.
Keywords:
dynamic compilation
binary translation
dynamic optimization
just-in-time compilation
adaptive code generation
profile-directed feedback
instruction-level parallelism
very long instruction word architectures
virtual machines
instruction set architectures
instruction set layering
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