EAVREF: An Evolutionary-Algorithm-Based Tool for Low-Power CMOS Voltage Reference Designs

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doi:10.1109/MDAT.2025.3600355

EAVREF: An Evolutionary-Algorithm-Based Tool for Low-Power CMOS Voltage Reference Designs

2026-04-01

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DOI：10.1109/MDAT.2025.3600355

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Editor's notes: This article presents an evolutionary-algorithm-based tool for robust low-power, low-voltage CMOS voltage reference design that accounts for process and mismatch variability. The tool is validated through post-layout results across multiple CMOS technologies using standard simulators and foundry process design kits. -Jose Augusto Nacif, Federal University of Vicosa, Brazil -Omar Paranaiba Vilela Neto, Federal University of Minas Gerais (UFMG), Brazil

Keywords:

Evolutionary computation

Monte Carlo methods

Graphical user interfaces

Voltage

Solid modeling

MOS devices

Temperature distribution

Regulation

Optimization

Next generation networking

Computer-aided tools

CMOS voltage references

low-power design

variability-aware design

wide-temperature range

EAVREF: An Evolutionary-Algorithm-Based Tool for Low-Power CMOS Voltage Reference Designs

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