.png){kind=icon}
.png){kind=icon}
Return
Effects of cell topology and JFET width on depletion layer of SiC MOSFET
.png){kind=icon}
PRE
AI
B
H
H
J
X
DOI：10.1088/1674-4926/25060030.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
High gate oxide electric field, which can lead to device failure, is a common issue in SiC MOSFETs. To mitigate this issue and ensure high device reliability, an electric field shielding layer (also called depletion layer) in JFET region is always used to reduce the gate oxide electric filed strength (Eox,max). However, there is still a lack of a detection methods to characterize the changes in the depletion layer of the JFET region. In this paper, a type of 1200 V 4H-SiC MOSFET with different JFET widths and cell topologies is designed and fabricated, and an innovative detection method for the depletion layer of JFET region is proposed for the first time. This method is adopted to focus on discussing the influence of the depletion layer formed by different JFET widths on Vg, and the changes in the gate oxide capacitance Cg of hexagonal cells and linear cells during the formation of the JFET depletion layer are studied. Finally, the robustness of different cell topologies and JFET widths is determined by the depletion voltage drift in the high temperature gate reverse bias tests (HTGB−) reliability test.
Keywords:
SiC MOSFET
depletion layer
JFET width
cell topology
electric field shielding
Journal
IF:
5.3
Papers:
277
Citations:
4.0K
Organization
Cited Papers