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Efficient associative processing in FPGA
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DOI：10.1016/j.micpro.2026.105257.png)
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Abstract
En 中文
In-memory processing can reduce data movement, alleviate the bottleneck between memory and processor, and improve performance and energy efficiency. Associative Processors (AP) in particular have demonstrated substantial performance gains. However, AP hardware designs with full arithmetic support are still limited, with existing implementations often inefficient or tailored to specific tasks, limiting evaluation across a broader range of applications. This paper presents the design and FPGA implementation of an AP that performs parallel bitwise logic, addition, subtraction, and multiplication directly in memory, making efficient use of LUTRAM and other FPGA logic elements. Using a RISC-V platform as a reference, we compare the AP with a traditional CPU and a vector processor, achieving up to 25x speedup over the CPU on a convolution kernel and an average 3x speedup over the vector processor while using fewer FPGA resources. Compared to a state-of-the-art AP, our implementation consumes 4x less power and requires only one-third of the hardware area.
Keywords:
Processing in memory
Associative processing
FPGA
RISC-V
Energy efficiency
Journal
M
IF:
2.6
Papers:
103
Citations:
3.2K