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Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes
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DOI：10.1109/TCSI.2011.2161416.png)
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Abstract
En 中文
Nonbinary LDPC codes are effective in combating burst errors. This paper presents an efficient architecture for implementing nonbinary LDPC decoders. The Galois field power representation is used to organize the a priori, a posteriori, and extrinsic messages involved in decoding. The power representation in conjunction with the barrel shifter and multithreaded pipelining yields an efficient implementation. The proposed decoder is configurable, in the sense that a single decoder can be used to decode any code of a given field size. The decoder supports both regular and irregular nonbinary QC-LDPC codes. Using a practical metric of throughput per unit area, the proposed implementation outperforms the best implementations published in research literature to date.
Keywords:
Configurable
decoder architecture
low-density parity-check (LDPC) codes
min-max
nonbinary
VLSI design
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5.2
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9.9K
Citations:
2.2W
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