Efficient Modular Addition for FPGA-Based Cryptographic Operations

Saeid Gorgin

doi:10.1109/TCAD.2025.3610064

Efficient Modular Addition for FPGA-Based Cryptographic Operations

2025-09-15

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DOI：10.1109/TCAD.2025.3610064

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Modular adders are essential components in finite field arithmetic, serving as key components in public-key cryptographic algorithms like elliptic curve cryptography (ECC) and postquantum cryptography (PQC). Naïve implementation of modular adders, due to two cascaded adders with large operand bit widths struggle to meet high-frequency requirements. On the other hand, parallel implementations, while faster, demand excessive resources and power, making them impractical for many applications. This article introduces a novel modular addition algorithm leveraging a novel operand representation based on the two-valued digit encoding (Twit). In this approach, each operand is represented as an $\boldsymbol {n}$ -bit unsigned number augmented by a twit value $\boldsymbol {\{0, \pm \delta \}}$ . The algorithm efficiently computes modular addition by speculating and dynamically adjusting the twit value in the result, achieving both computational and resource efficiency. The proposed design has been implemented on a Xilinx 7-series field-programmable gate array (FPGA), demonstrating superior performance in achieving high operating frequencies (i.e., 8%–36% depending on operand bit widths) while significantly reducing resource utilization (i.e., >36%). In addition to extensive analytical and synthesis-based evaluations, we further demonstrate the benefits of the proposed adder within application-level cryptographic datapaths (ECC and PQC).

Keywords:

Cryptographic operations

field-programmable gate array (FPGA)

finite field arithmetic

modular addition

two-valued digit representation

Efficient Modular Addition for FPGA-Based Cryptographic Operations

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