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Efficient power profiling for battery-driven embedded system design

delete2004-06-01
delete21
PRE
AI
K
Kanishka Lahiri
A
Anand Raghunathan
S
S. Dey
DOI：10.1109/TCAD.2004.828137delete
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Abstract

Abstract

En 中文
The ability to efficiently and accurately estimate battery life under different design choices at the system level is an important aid in designing battery-efficient systems. Recently developed battery models help by estimating battery life under given profiles of the battery discharge current over time. However, existing techniques for energy (or average power) estimation do not provide sufficient information (such as time profiles of system power consumption) to drive battery-life estimation. Techniques that are capable of generating such profiles often lack the efficiency required to support exploration at the system level. In this paper, we describe techniques for efficient generation of system-level power profiles, for use in a battery-life estimation framework. Our power profiling technique allows a designer to experiment with: 1) the mapping of system tasks to a set of architectural components and 2) the mapping of system communications to a specified communication architecture, and efficiently generate system power profiles for each alternative. The resulting profiles can then be analyzed using existing battery models to estimate battery lifetime and capacity. Extensive experiments conducted on an IEEE 802.11 MAC processor design demonstrate that our power profiler offers orders of magnitude improvement in runtimes over state-of-the-art cosimulation-based power estimation techniques, while suffering minimal loss of accuracy (average profiling error was 3.8%.
Keywords:
battery life estimation
hardware/software (HW/SW) mapping
low-power design
on-chip communication
system-level power estimation
system-on-chip
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Journal

I
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF:
2.9
Papers:
586
Citations:
9.6K

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