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Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design
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DOI：10.1109/TCAD.2025.3608005.png)
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Abstract
En 中文
Multiscalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof (ZKP) protocols. To address this, we introduce Fama, a field-programmable gate array (FPGA)-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, Fama minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, Fama achieves over 184.20 & times; speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64% and boosting area-time product (ATP) by up to 37.09 & times;.
Keywords:
Computational complexity
Parallel processing
Optimization
Three-dimensional displays
Protocols
Memory management
Heuristic algorithms
Field programmable gate arrays
Design automation
Arrays
Field-programmable gate array (FPGA)
hardware accelerator
multiscalar multiplication (MSM)
zero-knowledge proof (ZKP)
Journal
I
IF:
2.9
Papers:
564
Citations:
9.6K