Fault Testing Circuit and Algorithm for PCRAM Array Based on Temperature Regulation

doi:10.1109/TED.2026.3678157

Return

Fault Testing Circuit and Algorithm for PCRAM Array Based on Temperature Regulation

2026-04-01

PRE

DOI：10.1109/TED.2026.3678157

Original

Original request for help

Save

Abstract

En 中文

Emerging nonvolatile memories based on phase change memory (PCRAM) are expected to break through the performance bottlenecks of traditional memory systems. However, the intrinsic thermal sensitivity of phase change materials, coupled with the challenges of high-density integration, can easily induce special faults such as thermal interference and phase change threshold shift, causing to reliability degradation. To address these issues, this article proposes a temperature-regulated fault detection method based on a comprehensive thermal analysis of the device model. A simulation platform integrating defect-oriented (DO) and resistance defect (RD) models is established to support the design of a dual-path dynamic monitoring circuit. This circuit incorporates dual-margin comparators within a memory built-in self-test (MBIST) architecture, enabling real-time detection of compound faults through dynamic comparison of in-bitline (I_BL) and in-source line (I_SL) data paths. Additionally, a March-PCRAM fault detection algorithm is developed to exploit temperature gradients for activating fault-prone regions. Simulation and experimental results demonstrate that minor faults can be better detected through cyclic testing and temperature regulation, thereby reducing fault detection latency and enhancing test sensitivity. The proposed approach offers a robust testing framework and significantly improves the fault coverage of PCRAM arrays.

Keywords:

Fault injection

March algorithm

PCRAM

temperature regulation

test circuit