Gate stack engineering of two-dimensional transistors

doi:10.1038/s41928-025-01448-5

Gate stack engineering of two-dimensional transistors

2025-09-10

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DOI：10.1038/s41928-025-01448-5

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Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors. This Review examines the development of gate stack engineering technologies for two-dimensional (2D) transistors, benchmarking key performance metrics for such gate stacks against current silicon-based technologies and exploring the challenges that need to be addressed in order to create advanced electronic technologies based on 2D transistors.

Keywords:

two-dimensional transistors

gate stack engineering

semiconductor devices

ferroelectric materials

device scaling

Gate stack engineering of two-dimensional transistors

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