High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms

Hui Chen

doi:10.1109/TVLSI.2025.3590597

High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms

2025-07-24

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DOI：10.1109/TVLSI.2025.3590597

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Binary and decimal logarithms (BDLs) are commonly used in science and engineering. This brief presents a theory of the radix-4 generalized hyperbolic coordinate rotation digital computer (GH-CORDIC) to compute them directly. Compared with traditional hyperbolic CORDIC (TH-CORDIC), the two logarithms can be calculated without extra dividers or multipliers. Compared with the GH-CORDIC, this theory has low iterations under the same high precision. Through theoretical derivation and software simulation, we can find that the calculation accuracy can reach the magnitude of $10^{-7}$ , and the number of iterations can be reduced by more than 50%. Through hardware implementation, the synthesis report shows that the proposed architecture can save 53.44% area and 46.36% power consumption compared with the latest radix-2 GH-CORDIC method.

Keywords:

Binary logarithm

decimal logarithm

generalized hyperbolic coordinate rotation digital computer (GH-CORDIC)

high precision

low latency

radix-4

High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms

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