High-Throughput and Area-Efficient Parallel Multimode BCH Encoder

Hansol Jeong

doi:10.1109/tvlsi.2026.3722677

High-Throughput and Area-Efficient Parallel Multimode BCH Encoder

2026-08-18

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DOI：10.1109/tvlsi.2026.3722677

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This brief proposes a high-throughput, area-efficient parallel multimode Bose–Chaudhuri–Hocquenghem (BCH) encoder. The conventional multimode architecture relies on multiplexed feedback loops that create severe timing bottlenecks and hinder logic optimization in parallel implementations. The proposed encoder replaces the feedback multiplexer with a fixed feedback path by employing an AND-gate-based control method, enabling a unified matrix formulation and common subexpression elimination (CSE) across all error-correction modes. Synthesis results in 28-nm CMOS demonstrate up to 52% area reduction and up to 78% critical path delay reduction, resulting in higher achievable throughput under the same parallelization setting, compared to the conventional encoding architecture.

Keywords:

Bose–Chaudhuri–Hocquenghem (BCH) codes

hardware architecture

high-throughput architecture

multimode BCH encoder

parallel processing

High-Throughput and Area-Efficient Parallel Multimode BCH Encoder

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