Hypnos: A Hardware--Software Co-Design Framework for Memory-Efficient Homomorphic Processing

doi:10.1109/tcad.2026.3660206

Hypnos: A Hardware--Software Co-Design Framework for Memory-Efficient Homomorphic Processing

2026-02-02

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DOI：10.1109/tcad.2026.3660206

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Fully homomorphic encryption (FHE) introduces a novel paradigm in privacy-preserving computation, but operating on encrypted data imposes significant challenges, elevating data transmission, memory access demands, and programming complexity. Consequently, developing an efficient and usable system becomes vital. Conventional FHE accelerators often prioritize computational performance, typically assuming abundant encrypted data resides in accelerator memory. However, this perspective frequently overlooks the inefficiencies of the peripheral component interconnect express (PCIe) bus and main memory, alongside the complexities of optimizing for dedicated hardware in real-world deployments. This article proposes Hypnos, a hardware–software codesign framework for memory-efficient homomorphic processing. The Hypnos framework pairs a novel processing unit architecture with a dedicated Hypnos Compiler. In architecture, the heterogeneous processing unit based on homomorphic encryption uses a paging memory management system to reduce memory fragmentation and optimize the PCIe traffic. In software, the Hypnos compiler is able to automatically translate high-level FHE schemes into optimized hardware commands. It schedules the data placement in cooperation with our memory management system to effectively harness the performance of hardware. This codesign of hardware and compiler not only reduces memory access and execution time but also lowers the complexity of deploying FHE applications. Finally, We implement Hypnos on the QianKun field-programmable gate array (FPGA) Card and highlight the following results: 1) outperforms state-of-the-art (SOTA) application-specific integrated circuit (ASIC) and FPGA solutions in data-intensive applications by up to $2.75\times $ and $4.72\times $ ; 2) the communication overhead is reduced by $4.85\times $ compared to traditional architectures; and 3) up to $30.1\times $ and $20.7\times $ energy efficiency improvement compared to ASIC-based ARK and FPGA-based Poseidon for ResNet-20, respectively.

Keywords:

Field-programmable gate array (FPGA)

fully homomorphic encryption (FHE)

memory efficient

peripheral component interconnect express (PCIe)

Hypnos: A Hardware--Software Co-Design Framework for Memory-Efficient Homomorphic Processing

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