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Impact of Maximum Process Temperature on Negative Bias Temperature Instability in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors
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DOI：10.1109/ted.2026.3708821.png)
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Abstract
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This study investigates the effect of the maximum process temperature on bias-temperature-instability-like degradation in p-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). Devices fabricated at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400~^{\circ }$ </tex-math></inline-formula>C, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$370~^{\circ }$ </tex-math></inline-formula>C, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$350~^{\circ }$ </tex-math></inline-formula>C show comparable initial threshold voltage and subthreshold swing owing to the identical process flow and postfabrication hydrogen annealing. Under negative gate bias temperature stress, lower process-temperature devices exhibit a larger threshold voltage shifts, stronger subthreshold swing degradation, and lower extracted the effective activation energy. These results indicate that maximum process temperature has a limited impact on the initially observable threshold voltage and subthreshold swing, but critically affects long-term reliability.
Keywords:
Bias temperature instability (BTI)
device reliability
low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs)
negative bias temperature stress
process temperature dependence
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