Implementation of imprecise multipliers using 2-bit adder for image processing

doi:10.1016/j.vlsi.2025.102510

Implementation of imprecise multipliers using 2-bit adder for image processing

2025-09-01

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Parthibaraj Anguraj *

T

Thiruvenkadam Krishnan

DOI：10.1016/j.vlsi.2025.102510

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The inexact multiplier architecture represents a foundational element of approximate computing, serving a critical function across diverse error-tolerant applications. This paper delves into the complexities of three distinct inexact multiplier designs, each meticulously optimized for image processing applications. This work introduces a strategic partitioning of the partial product stage into smaller segments, subsequently implementing decoder algorithms, truncation methods, exact 2-bit adder and proposed multiplexer-based imprecise 2-bit adder circuits. These resulting 8x 8 imprecise multipliers exhibit advantageous error metrics and streamlined design complexity. When benchmarked against traditional inexact multipliers, these architectures achieve notable reductions in both area and power consumption, as validated by modeling conducted via the Cadence RTL compiler with TSMC's 90 nm technology. The proposed approximation model demonstrates substantial area and power reductions of 37.19% and 46.14%, respectively, compared to precise multipliers, all while sustaining acceptable error metrics. Additionally, the developed 8x 8 multipliers surpass other approximate multiplier architectures in performance metrics, making them particularly effective for image multiplication and sharpening.

Keywords:

Approximate methodology

2-bit adder

Area

Delay and power requirements

Implementation of imprecise multipliers using 2-bit adder for image processing

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